Ian O CONNOR

Informations personnelles

Ian O CONNOR

Professeur des Universités ECL

Localisation	INL Site Ecole Centrale de Lyon Batiment F7 36, Avenue Guy de Collongue 69134 Ecully France
Téléphone	(33).04 72 18 60 54
Courriel	ian.oconnor@ec-lyon.fr

Activités de recherche Publications

Activités de recherche

Département : Electronique

Equipe de recherche : Conception de Systèmes Hétérogènes

Domaine d'activités :
Méthodes et outils de conception de systèmes sur puce hétérogènes Architectures de circuits à base de nanocomposants Interconnexions optiques intégrées Circuits intégrés 3D

C.V.

Ian O'Connor (IEEE S'95-M'98-SM'07, IEE S'87-M'98) est né à Cambridge, Royaume-Uni, en 1969. Il a obtenu les diplômes de B. Eng. Electronics Engineering (Université d'Essex, Royaume-Uni) en 1990 ; le European M.Sc. Electronics Engineering (diplôme décerné conjointement par l'Université d'Essex, Royaume-Uni, Ecole Supérieure d'Ingénieurs d'Electronique et d'Electrotechnique (ESIEE), Paris, France, et l'Université de Karlsruhe, Allemagne) en 1992 ; le Doctorat en Electronique (Université de Lille, France) en 1997 ; et l'Habilitation à Diriger des Recherches (Ecole Centrale de Lyon, France) en 2005. De 1993-1997 il était assistant d'enseignement et de recherche à l'Institut Supérieur d'Electronique du Nord, France et de 1997-1998, il était ingénieur principal en CAO chez Philips Semiconductors (aujourd'hui NXP Semiconductors), Royaume-Uni. Il a rejoint l'Ecole Centrale De Lyon en 1998 en tant que Maître de Conférences dans le département Electronique, Electrotechnique et Automatique. Il est actuellement responsable de l'équipe Conception de Systèmes Hétéorgènes à l'Institut des Nanotechnologies de Lyon. Depuis 2008, il occupe également un poste de professeur associé à l'Ecole Polytechnique de Montréal, Canada. Ses travaux de recherche concernent l'élaboration de methodes et d'outils de conception pour systèmes sur puce physiquement hétérogènes, ainsi que leur application aux architectures nouvelles basées sur des dispositifs non-conventionnels (réseaux optiques sur puce, nanoprocesseurs à base de CNTFET, architectures intégrées 3D). Il est auteur ou co-auteur d'environ 100 chapitres d'ouvrage, articles de journal et conférences, et a été responsable de workpackage ou coordinateur scientifique pour plusieurs projets nationaux et européens. Il est actuellement expert à l'Observatoire des Micro- et Nano-Technologies (OMNT).

Publications des 5 dernières années

Articles dans des revues internationales ou nationales avec comité de lecture répertoriées par l’AERES ou dans les bases de données internationales (12 publications)

An efficient and simple compact modeling approach for 3-D interconnects with IC's stack global electrical context consideration
LORIVAL J., CALMON F., SUN F., FRANTZ F., PLOSSU C., LE BERRE M., O CONNOR I., VALORGE O., CHARBONNIER J., HENRY D., GONTRAND C.,
Microelectronics Journal, 46 (2)-153-165 (2015)
Introducing photonic devices for 40Gbits/s wavelength division multiplexing transceivers on 300-mm SOI wafers using CMOS processes
BAUDOT C., FEDELI J.M., MARRIS-MORINI D., CAIRE-REMONNAY B., VIROT L., OLIVIER S., MYKO A., GROSSE P., GRAND G., BEN BAKIR B., HARTMANN J., ALLOUTI N., BARNOLA S., VIZIOZ C., RIVOIRE M., SEIGNARD A., SOUHAITé A., O CONNOR I., VIVIEN L., MENEZO S.,
Integrated Optics: Devices, Materials, and Technologies, 8988-89880O-1 – 89880O-16 (2014)
Modeling and Simulation of Networked Low Power Embedded Systems: a Taxonomy
DU W., MIEYEVILLE F., NAVARRO D., O CONNOR I., CARREL L.,
EURASIP Journal on Wireless Communications and Networking, - (2014)
Design and Architectural Assessment of 3-D Resistive Memory Technologies in FPGAs
GAILLARDON P., SACCHETTO D., BENEVENTI G., BEN JAMAA M., PERNIOLA L., CLERMIDY F., O CONNOR I., DE MICHELI G.,
IEEE Transactions on Nanotechnology, 12-40-50 (2013)
Functions classification approach to generate reconfigurable fine-grain logic based on Ambipolar Independent Double Gate FET (Am-IDGFET)
Functions classification approach to generate reconfigurable fine-grain logic based on Ambipolar Independent Double Gate FET (Am-IDGFET)
JABEUR K., O CONNOR I., YAKYMETS N.,
Am-IDGFET is a new family of particular devices in view of the fact that it associates three benefits: (i) it is usually a 1-D electronic device (CNT or SiNW), meaning high mobility, achievable current density and high I-ON/I-OFF ratio; (ii) Independently controlled gates which offers the device extra logic options; (iii) ambipolar behaviour opens the way for N- and P-type polarities in the same device via its back gate. The creativity of this work consists of looking at this new class of emerging technology as an opportunity for new design paradigms with no equivalent counterparts in CMOS technology. Nevertheless, to build a feasible and complete picture of ambipolar logic, innovative design approaches and tools are required. In this paper, we exploit functional classification, a powerful tool for the construction and analysis of Boolean functions, to build reconfigurable logic blocks by defining a hierarchical correlation between structures of functions classes with ambipolar devices. We demonstrate how this approach enables us to build Am-I DGFET-based n-input reconfigurable cells. Several dynamically reconfigurable 2-inputs logic cells with partial and full functionality are designed in this paper. We evaluate the performances of circuits designed from this approach in a case study focused on Double Gate Carbon Nanotube FET (DG-CNTFET) technology. Simulations results show efficiency to build fine grain reconfigurable cells with partial functionality. In the case of 9-functions reconfigurable cell, an improvement of 1.8X in terms of power delay product (PDP) is proved when compared to a CMOS-16 nm technology. Fewer control signals are required and the area is reduced by 35% over CMOS technology. (C) 2013 Elsevier Ltd. All rights reserved. ×
[abstract]
JABEUR K., O CONNOR I., YAKYMETS N.,
Microelectronics Journal, 44 - 12- 1316-1327 (2013)
Functions classification approach to generate reconfigurable fine-grain logic based on Ambipolar Independent Double Gate FET (Am-IDGFET)
JABEUR K., O CONNOR I., YAKYMETS N.,
Microelectronics Journal, 44-1316-1327 (2013)
Image Toolbox for CMOS Image Sensors Fast Simulation
NAVARRO D., FENG Z., O CONNOR I.,
Global Journal of Computer Science and Technology, - (2013)
iMASKO: A Genetic Algorithm Based Optimization Framework for Wireless Sensor Networks
ZHU N., O CONNOR I.,
Journal of Sensor and Actuator Networks, 2-675-599 (2013)
Reduction methods for adapting optical network on chip topologies to 3D architectures
Reduction methods for adapting optical network on chip topologies to 3D architectures
LE BEUX S., O CONNOR I., NICOLESCU G., BOIS G., PAULIN P.,
Optical Network on Chip (ONoC) architectures are emerging as promising candidates to solve congestion and latency issues in future embedded systems. In this work, we examine how a scalable and fully connected ONoC topology can be reduced to fit specific connectivity requirements in heterogeneous 3D architectures. Through such techniques, it is possible to reduce the number of required wavelengths, laser sources, photodetectors and optical switches as well as the length of the longest optical path. This allows constraints to be relaxed on source wavelength accuracy and passive filter selectivity, and also alleviates power and area issues by reducing the number of active devices. The proposed reduction method was successfully applied to multiple heterogeneous 3D architectures. (c) 2012 Elsevier B.V. All rights reserved. ×
[abstract]
LE BEUX S., O CONNOR I., NICOLESCU G., BOIS G., PAULIN P.,
Microprocess. Microsyst., 37, 1-87-98 (2013)
Reduction methods for adapting optical network on chip topologies to 3D architectures
LE BEUX S., O CONNOR I., NICOLESCU G., BOIS G., PAULIN P.,
Elsevier Microprocessors and Microsystems - Embedded Hardware Design, 37-87-98 (2013)
SystemC fine-grained HW-SW fully heterogeneous WSN simulation and UML metamodel behavioural extraction
SystemC fine-grained HW-SW fully heterogeneous WSN simulation and UML metamodel behavioural extraction
GALOS M., MIEYEVILLE F., NAVARRO D., O CONNOR I.,
Wireless sensor networks are becoming an essential part of our lives, being frequently used for monitoring and control applications. It is essential that these networks be modelled before their deployment so as to identify the possible problems that may arise. SystemC is fast becoming an important modelling paradigm in the context of SoC design and verification, as well as other fields that require accurate (sometimes Transaction Level Modelled) characterization of digital processes (i.e.: communication on a bus interface, over a radio channel, etc). SystemC has successfully been used in the IDEA1 WSN exploration framework to model wireless sensor networks at the timed functional level of abstraction. As a first contribution, we refined the initial implementation of IDEA1 to cope with a finer-grade simulation of the node hardware, going beyond the timed functional description of the node and enabling support for a bus cycle-accurate simulation. The new and improved version is called IDEA1TLM and can also model the software aspect of the nodes in question by means of a custom-built instruction set simulator called BLISS. The second part of this contribution focuses on extracting the metamodel from SystemC source files. The metamodel is the information which can be generated concerning the model; in our case, a diagram representation with states and transitions between them. Because current work focuses on generating C++ code (SystemC-compliant) from UML metamodels, there is no support to achieve this in reverse. We developed a tool called DiaSig that takes SystemC source files as input and generates UML diagrams of the model in SVG format. ×
[abstract]
GALOS M., MIEYEVILLE F., NAVARRO D., O CONNOR I.,
Analog Integrated Circuits and Signal Processing, 77 - 2-123-133 (2013)
SystemC fine-grained HW–SW fully heterogeneous WSN simulation and UML metamodel behavioural extraction
GALOS M., MIEYEVILLE F., NAVARRO D., O CONNOR I.,
Analog Integrated Circuits and Signal Processing, 77-123-133 (2013)

Communications avec actes dans un congrès international (5 publications)

Multilevel Modeling Methodology For Reconfigurable Computing Systems Based On Silicon Photonics
LI Z., LE BEUX S., MONAT C., LETARTRE X., O CONNOR I., , , , , , , , , , , , , , , ,
2015 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) 8-10 juillet Montpellier (France) (2015)
3D Integration of CMOS Image Sensor with Coprocessor Using TSV last and Micro-Bumps Technologies
COUDRAIN P., HENRY D., BERTHELOT A., CHARBONNIER J., VERRUN S., FRANIATTE R., BOUZAIDA N., CIBRARIO G., O CONNOR I., O CONNOR I., LACREVAZ T., FOURNEAUD L., FLECHET B., CHEVRIER N., FARCY A., LE-BRIZ O.,
Electronic Components and Technology Conference (ECTC) May 28 - 31, 2013 Las Vegas, USA (2013)
3D Integration of CMOS Image Sensor with Coprocessor Using TSV last and Micro-Bumps Technologies
COUDRAIN P., HENRY D., BERTHELOT A., CHARBONNIER J., VERRUN S., FRANIATTE R., BOUZAIDA N., CIBRARIO G., CALMON F., O CONNOR I., LE-BRIZ O., FOURNEAUD L., FLECHET B., CHEVRIER N., FARCY A.,
Electronic Components and Technology Conference (ECTC) May 28 - 31, 2013 Las Vegas, USA (2013)
Energy Measurements and Evaluations on High Data Rate and Ultra Low Power WSN Node
Energy Measurements and Evaluations on High Data Rate and Ultra Low Power WSN Node
ZHU N., O CONNOR I.,
Due to reliance on batteries, energy consumption has always been of significant concern for sensor node networks. While many energy efficient protocols and energy-aware application scenarios have been proposed in recent years, most are based on unrealistic theoretical model analyses or simple simulations due to the lack of real-world energy measurement tools, which leads to erroneous energy consumption prediction. Therefore, the energy source of sensor networks may be exhausted before completion of the required task. This paper presents our experimental platform named iWEEP_HW, which consists of Multichannel Energy Measurement Device (MEMD), Energy Data Management Software Platform (EDMSP) and a Testbed node. By using MEMD and EDMSP, real-world measurements and corresponding analyses are provided based on our high data-rate and ultra low-power testbed iHop Node. Such measurements, as well as the measurement protocol, could be valuable for other researchers focusing on energy efficiency in WSNs, and the provided measurements can also be used as a simulated energy model. ×
[abstract]
ZHU N., O CONNOR I.,
10th IEEE International Conference on Networking, Sensing and Control (ICNSC) APR 10-12, 2013 Evry Val Essonne Univ, France (2013)
Performance Evaluations of unslotted CSMA/CA Algorithm at High Data Rate WSNs Scenario
Performance Evaluations of unslotted CSMA/CA Algorithm at High Data Rate WSNs Scenario
ZHU N., O CONNOR I.,
As a leading standard in wireless sensor networks, IEEE 802.15.4 based networks are well-adapted to various applications such as environment monitoring, building automation and medical/health care, in which sensor nodes are always densely deployed and with the intense channel competition. However, the use of 250Kbps low-rate based network that defined in the standard can be inefficiency for these applications. Therefore, in this paper with nRF24 transceiver that supports high data rate over the air transmission and reception, we analyse the packet loss and lifetime estimation of a high data rate network via SystemC simulations by using unslotted algorithm in 1Mbps and 2Mbps scenarios. The impact of macMinBE / macMaxBE (BE), macMaxCSMABackoffs(Backoff) and macMaxFrameRetries (Retries) are performed under different traffic loads and at 1Mbps and 2Mbps high rate along with 250Kbps low rate. Experimental results show that the use of greater BE under different traffic loads of three data rates, and smaller Backoff at high traffic loads under 250Kbps and 1Mbps are able to achieve better lifetime and less packet loss. For Retries, the use of a greater value under low traffic loads of 1Mbps and 2Mbps can provide a good trade-off between lifetime performance and packet loss. On the other hand, we also deepen the analysis to include the nRF24 transceiver s embedded communication protocol engine Enhanced ShockBurst (ESB) forcomparison. Furthermore, we also provide suggestions on the trade-off between packet loss and lifetime after each scenario analysis. ×
[abstract]
ZHU N., O CONNOR I.,
9th International Wireless Communications and Mobile Computing Conference (IWCMC) JUL 01-05, 2013 Cagliari, Italy (2013)

Ouvrages scientifiques (ou chapitres de ces ouvrages) (1 publication)

Thermal-Aware Design Method for On-Chip Laser-based Optical Interconnect
LI H., FOURMIGUE A., LE BEUX S., LETARTRE X., O CONNOR I., NICOLESCU G., , , , , , , , , , , , , , ,
Photonic Interconnects for Computing Systems: Understanding and Pushing Design Challenges River Publishers Series in Optics and Photonics (2017)